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Hi burnmeister, Can you give a few more details, why is the speed important, what sort of ADC etc.
Siemens – datasheet pdf
If you have same good ideas, please go on Finally, the filter output data is sampled read out every 16 conversions i. There is not enough time to read the 16bit like this: Using a bit latch would only add to your delay.
Hi burnmeister Without personally knowing your ADC chip, my guess is that the output is bsx125 in tri-state until either or both of the RD and CS lines are pulled low.
You may miss the first value, but that’s OK – you’re looking for the impulse response over several dozen readings.
Otherwise there are only 4 ‘ instruction cycles available. In that case – and assuming you can solve the synchronization problem between DRDY and the ‘ instruction cycle – there are just enough instruction bss1225 to work. I can’t be sure to catch the impuls cause it’s only during for ns.
Why does my PIC32 run slower than expected? Haven’t received registration validation E-mail? I hope the circuit will run next monday.
I cant say anything else about ‘timings’ because there’s no detailed information here of the signal you have to make digital. One Thing I still don’t understand: The fastest pin-sampling loop I can think of is: I am not certain that I understand this correctly, but the Data Sheet doesn’t seem to have any other ways to interpret that specification. That is a species I have never encountered in the wild.
BSS (Siemens) – Sipmos Small-signal Transistor (n Channel Enhancement Mode), N-Channel
I have looked at the AD Data Sheet. From “Circuit Description” in the Data Sheet: Do you know the English word “stumped”? I think you should be more concerned about the other more prominant delays like the ADC conversion and acquisition, time taken to perform calculations on the data or to display it Trigger the microcontroller program off the square wave edge: The modulator output is processed by a finite impulse response FIR digital filter.
Allow me to add my comments to the confusion. It was invented, as the Data Sheet says, to put us grey-haired analog filter designers out of work. I see there is an expert on the other line Each time you get the detection, why not perform a wait by using a fixed number of NOP instructions 4 so that you would end up just past the start of lo DRDY on the next AD cycle, then do your code below. Sorry for my english, i’m from Switzerland German langague Greets burnmeister.
Again a big Thanks for your ideas and help!!!! This includes the rise time of the signal source photodiode array plus the rise time of any anti-aliasing network on the analog input. I don’t know how this fits in with you required sample rate, but you have as long as you need to take a sample. The AD is sampling continuously. I can’t take a 16 bit latch to buffer the values, cause my design is already produced I’m surprised by your statement: Forum Themes Elegant Mobile.
When i’m looking for the high period of DRDY with some code like this: My understanding of the diagrams is this: Gixy Super Member Total Posts: This might be useful for solving the sync problem.
THX a lot for your detailed answer dchisholm!!!
SS125 Datasheet, Equivalent, Cross Reference Search
It would be very glad, if anyone can help me to understand the bzs125 timing diagramm. According to the Data Sheet Section This architecture of oversample-then-decimate-in-the-data-domain seems to be fairly common. Essentials Only Full Version. It might be time to do an experiment in your development lab. Guest Super Member Total Posts: Forums Posts Latest Posts. I am not certain that timing diagram Figure 7b is correct for your application.
You already listed the fastest way to read two ports: